In this section, we will first learn about pipeline stalling. After that, we will learn about types of pipeline delays.

Pipeline Stalling

A pipeline stalling can be described as an error in the RISC. Due to the stalling, the processing of instruction will be delayed. This type of error and the user errors are not similar to each. The stalls are basically generated due to the poorly designed processor. The pipelines are used by the RISC processor, which shows that a specific order is used to execute the instructions.

If there is a program that provides us a branching instruction, they will not present in an orderly fashion. In the starting, instructions work their way with the help of pipeline, but before proceeding to the next instruction, it has to discard the options that were not selected. Because of this, a delay is generated. There will be more delay if the discarded options are more. The lap in the performance will be huge if there is a big amount of delay.

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Common use of Pipeline Stall

• With the help of implementation of branch predication, the pipeline stall can be resolved.
• The potential of pipeline stall is determined by the downside of RISC processor.

Misuse of Pipeline Stall

• When a user executes several functions at the same time, in this case, the pipeline stalls will occur.

Types of Pipeline delay

The pipeline delay is of two types, which are described as follows:

1. Uniform Delay Pipeline

All the stages in a uniform delay pipeline will complete their operations by taking the same time. The cycle time in this pipeline is described as follows:

Cycle Time (Tp) = Stage Delay

If there are buffers between the stages, then the cycle time will be described as follows:

Cycle time (Tp) = Stage Delay + Buffer Delay

2. Non-uniform Delay Pipeline

All the stages in a non-uniform delay pipeline will complete their operations by taking different times. The cycle time in this pipeline is described as follows:

Cycle Time (Tp) = Maximum (Stage Delay)

For example: Suppose we have four stages, which contain stage delay as 1 ns, 2 ns, 3 ns, and 4 ns. In this case, the cycle time will be:

Tp = Maximum (1 ns, 2 ns, 3 ns, 4 ns) = 4 ns

If there are buffers between the stages, then the cycle time will be described as follows:

Cycle time (Tp) = Maximum (Stage Delay + Buffer Delay)

Example: In this example, we will assume 4 segment pipeline which contains stage delay as 2 ns, 8 ns, 3 ns, 10 ns. Here we have to determine the time which is taken to execute 100 tasks in the above pipeline.

Solution:

As we can see, the above pipeline is a type of non-linear pipeline. So for this pipeline, the cycle time is described as follows:

Tp = max(2, 8, 3, 10) = 10 ns
As we know that ET pipeline = (k + n - 1) Tp = (4 + 100 -1) 10 ns = 1030 ns

Note: MIPS stands for Million instructions per second

Performance of Pipeline with stalls

We can find out the performance of pipeline with stalls with the help of following formula:

Speed up (S) = Performance pipeline / Performance non-pipeline
       S = Average Execution Time nonpipeline / Average Execution Time pipeline
       S = CPI non-pipeline * Cycle Time non-pipeline / CPI pipeline * Cycle Time pipeline

In the pipelined processor, the ideal CPI is 1. But because of the stalls, these CPI becomes greater than 1.

S = CPI non-pipeline * Cycle Time non-pipeline / (1 + Number of stalls per Instruction) * Cycle Time pipeline
As Cycle Time non-pipeline = Cycle Time pipeline
Speed Up (S) = CPI non-pipeline / (1 + Number of stalls per instruction)

The pipelines are used by the RISC processor that means with the help of a specific order, we can execute the instructions.